Method for processing a semiconductor substrate having a copper surface disposed thereon and structure formed

ABSTRACT

A semiconductor wafer having copper bondpads ( 17 ) that are free of voids ( 13 ) and a method for coating the copper bondpads ( 17 ) with solderable or wirebondable metals such that the copper bondpads ( 17 ) are free of the voids ( 13 ). The void free metal coatings are achieved using a dual activation process. In a first activation step ( 27 ), the copper bondpads ( 17 ) are activated by placing them in a palladium bath. In a second activation step ( 28 ), the bondpads are placed in a nickel—boron bath. After the dual activation, the copper bondpads ( 17 ) are coated with a layer of nickel—phosphorous or palladium. The nickel—phosphorous or palladium layer may be coated with a layer of gold for subsequent formation of solder balls or wirebonds thereon.

BACKGROUND OF THE INVENTION

[0001] The present invention relates, in general, to metallizationsystems and, more particularly, to copper metallization systems.

[0002] Monolithically integrated circuits typically include multiplelayers of metal that terminate in bondpads through which electricalsignals are transmitted. In the past, the multiple layers of metal havebeen formed from aluminum. However, semiconductor manufacturers havebegun using copper, rather than aluminum, because of copper's superiorelectromigration performance as well as its lower resistivity. Inaddition, a copper metallization process can actually lead to lowermanufacturing costs than aluminum.

[0003] Although there are many advantages to using copper, its surfaceis not suitable as a terminal metal for packaging interconnections.Separate coating metals are needed to deposit onto the copper bond padsfor packaging interconnections. One method is direct deposition of metalonto copper bond pads by an electroless deposition technique such aselectroless nickel followed by immersion in gold for flip chipapplications and/or electroless palladium deposition followed byimmersion gold in for wirebond applications. For such depositiontechniques, the copper surface is generally activated with a very thinlayer of palladium in a palladium activation bath to allow deposition ofa nickel layer thereon. In this step, the palladium covers the copper sothat nickel can be electrolessly plated on the layer of palladium. Whenthe palladium only partially covers the copper, a galvanic cell is setup that results in preferential etching at the copper—palladium grainboundaries. The preferential etching causes voids in the copper andundercutting at the interface between the copper and palladium.

[0004]FIG. 1 is a highly enlarged cross-sectional view of asemiconductor wafer 10 having a copper bondpad 11 disposed thereon. Alayer 12 of nickel is disposed on copper bondpad 11. Copper bondpad 11has voids 13 at the interface between the copper and nickel layerscaused by the use of palladium to activate the copper surface. Voids 13lower the shear values of the interface, increase the probability ofsodium contamination, and create electromigration problems.

[0005] Accordingly, it would be advantageous to have a method forelectrolessly plating metals on a copper surface that is cost efficientand suitable for use in an integrated circuit manufacturing process. Itwould be desirable to have a semiconductor structure on which a copperbondpad is disposed that is void-free, i.e., does not have voids, and amethod for manufacturing this structure. It would be of furtheradvantage for the method to be suitable for use at temperatures lessthan about 90 degrees Celsius.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006]FIG. 1 is a highly enlarged cross-sectional view of asemiconductor wafer having copper bondpads disposed thereon, whereinvoids are present at a copper—nickel interface;

[0007]FIG. 2 is a highly enlarged cross-sectional view of asemiconductor wafer having copper bond pads disposed thereon;

[0008]FIG. 3 is a flow diagram of a process flow for treating a coppersurface in accordance with a first embodiment of the present invention;

[0009]FIG. 4 is a flow diagram of a process flow for treating a coppersurface in accordance with a second embodiment of the present invention;and

[0010]FIG. 5 is a highly enlarged cross-sectional view of asemiconductor wafer having copper bondpads disposed thereon processed inaccordance with the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

[0011] Generally, the present invention includes a method for forming ametal such as nickel—phosphorous or palladium on a copper surface thatis disposed on a semiconductor wafer such that voids are not formed inthe copper or at the interface between the copper and nickel. The methoduses a dual activation process that includes formation of a layer ofpalladium on the copper and a layer of nickel—boron on the layer ofpalladium. A layer of nickel—phosphorous or palladium is formed on thenickel—boron layer. Using the dual activation process produces copperbondpads that do not have voids formed therein. In addition, the presentinvention is suitable for use in applications that use solder balls aswell as applications that use wirebonds.

[0012]FIG. 2 is a cross-sectional view of a substrate such as, forexample, a semiconductor wafer 15 having copper bondpads 17 formedthereon. Although the copper interconnects structures are shown as twobondpads, it should be understood this has been done to aid indescribing the present invention. Copper bondpads 17 also representmulti-layer interconnect structures.

[0013]FIG. 3 is a flow diagram 20 of a process flow for treating coppersurfaces 16, such as for example, surfaces 16 of copper bondpads 17, inaccordance with a first embodiment of the present invention. The processflow illustrated by flow diagram 20 is particularly useful for formingan underbump metallization system on copper surfaces 16. In a first step21, semiconductor wafer 15 is placed in a plasma etcher and an oxygenplasma is used to remove or clean any organic contaminants from coppersurfaces 16. In a second step 22, wafer 15 is placed in a wet etchingbath to remove inorganic contaminants. By way of example, the wetetching bath is a buffered oxide etchant.

[0014] After removing the organic and inorganic contaminants from coppersurfaces 16, it may be desirable to remove any cupric oxide that mayhave formed on copper surfaces 16. Therefore, a cupric oxide removalstep 23 is performed by placing semiconductor wafer 15 in a persulfatebath followed by sulfuric acid bath.

[0015] After copper surfaces 16 have been cleaned, they are activated byplacing semiconductor wafer 15 in a palladium activation bath. TABLE 1lists the ingredients for the palladium activation bath. TABLE 1Palladium Sulfate ˜75mg/l to ˜175mg/l (Pd⁺⁺SO₄ ⁻⁻) sulfuric acid ˜3% to˜8% by volume (H₂SO₄) Operating Temperature ˜20° C. to ˜30° C.

[0016] It should be noted that the symbol ˜ is shorthand notation for“approximately”, mg/l stands for milligrams per liter, and ° C. standsfor degrees Celsius. It should be noted that the units mg/l are alsoreferred to as parts per million (ppm).

[0017] By way of example, semiconductor wafer 15 is placed in apalladium bath containing approximately 100 mg/l of palladium sulfateand approximately 5% sulfuric acid by volume for approximately 30seconds. The palladium reacts with copper surfaces 16 to allow a metalsuch as, for example, nickel, to be plated on the palladium. Thus, thepalladium activation step, identified by reference numeral 27, createsreaction sites on copper surfaces 16 that are more susceptible toreaction with the plating nickel metal than pure copper.

[0018] After activating copper surfaces 16 with palladium, the surfacesare activated a second time in an electroless nickel—boron bath having aconcentration of lead that is less than approximately 5 mg/l. By way ofexample, the concentration of lead is between approximately 1 mg/l andapproximately 3 mg/l. It is important to keep the lead concentrations ator below 5 mg/l when plating nickel on palladium activated coppersurfaces that is formed on a semiconductor wafer because the lead actsas a deactivating agent. In other words, using lead concentrationsgreater than 5 mg/l when plating nickel on semiconductor wafers causesskip-plating. This second activation step is identified by referencenumeral 28.

[0019] Semiconductor wafer 15 is left in the bath long enough to depositfrom approximately 0.1 microns to approximately 0.5 microns ofnickel—boron. A suitable amount of time to accomplish this deposition isbetween approximately 1 and 5 minutes, with a nominal time ofapproximately 2 minutes.

[0020] After completing the second activation step (Identified byreference numeral 28), semiconductor wafer 15 is placed in asubstantially lead-free electroless nickel-phosphorous bath. This stepis identified by reference numeral 29.

[0021] By way of example, semiconductor wafer 15 is left in the bathlong enough to deposit from approximately 6 microns to approximately 9microns of nickel—phosphorous. A suitable amount of time to accomplishthis deposition is between approximately 30 and 45 minutes, with anominal time of approximately 30 minutes.

[0022] After the nickel—phosphorous layer has been plated on thenickel—boron layer, a layer of gold is deposited on thenickel—phosphorous layer to protect it from oxidation. The layer of goldis also referred to as an oxidation protection layer. This step isidentified by reference numeral 31. Preferably, the thickness of thegold layer is between approximately 0.03 microns and 0.06 microns.Techniques for forming a layer of gold on a layer of nickel—phosphorousare well known to those skilled in the art.

[0023] Solder balls are formed on the gold layer using techniques wellknown to those skilled in the art.

[0024]FIG. 4 is a flow diagram 40 of a process flow for treating acopper surface, such as for example, copper surfaces 16, in accordancewith a second embodiment of the present invention. The process flowillustrated by flow diagram 40 is particularly useful for forming ametallization system on copper surfaces 16 to which wirebonds can beformed. It should be noted that the steps identified by referencenumbers 21, 22, 23, 24, 27, and 28 are the same as those used for theembodiment in which an underbump metallization system was formed. Itshould be further noted that the same reference numerals are used torepresent similar elements. Thus, the second embodiment has beendescribed with the assumption that the electroless nickel—boron layerhas been formed.

[0025] At the step identified by reference numeral 41, an electrolesspalladium layer is formed on the electroless nickel—boron layer. Theelectroless palladium layer is formed by placing semiconductor wafer 15in an electrcless palladium bath.

[0026] Semiconductor wafer 15 is left in the bath long enough to depositfrom approximately 0.4 microns to approximately 0.8 microns of palladiumon the electroless nickel—boron layer. A suitable amount of time toaccomplish this deposition is between approximately 30 and 60 minutes,with a nominal time of approximately 30 minutes.

[0027] After the palladium layer has been plated on the nickel—boronlayer, an optional layer of gold is deposited on the palladium layer toprotect it from oxidation. This step is identified by reference numeral42. Preferably, the thickness of the gold layer is between approximately0.03 and 0.06 microns. Techniques for forming a layer of gold on a layerof nickel—phosphorous are well known to those skilled in the art.

[0028] Wirebonds are formed on the gold layer using techniques wellknown to those skilled in the art. Again, it should be understood thatforming the layer of gold on the electroless palladium is an optionalstep. Thus, the wirebonds can be formed directly on the electrolesspalladium layer.

[0029]FIG. 5 is a highly enlarged cross-sectional view of asemiconductor wafer having copper bondpads disposed thereon andprocessed in accordance with the present invention. It should be notedthat the voids present in FIG. 1 are not present in semiconductor wafersmanufactured in accordance with the present invention.

[0030] By now it should be appreciated that a method for processing awafer having copper bondpads that does not produce voids in the copperhas been provided. An important aspect of the present invention isrecognizing the need for an electroless nickel bath having a lowconcentration of lead. The method entails the use of a dual activationprocess that allows processing the wafer at temperatures less than about90° C. Using the low temperatures set forth in the present inventionallows formation of reliable copper interconnects on a semiconductorwafer. In addition, eliminating the copper voids enables the use of verythin copper interconnects for highly dense integrated circuits. Further,eliminating the copper voids increases bond shear strength and bond pullstrength between the copper and nickel interface which improves longterm reliability. Additionally, the dual activation process enhances thecapability of ultra fine pitch plating.

1. A method for processing a semiconductor substrate having a coppersurface disposed thereon in preparation for subsequent bondingoperations, comprising the steps of: providing the semiconductorsubstrate having copper disposed thereon, the copper having a bondingsurface; cleaning the bonding surface; activating the bonding surfacefirst activation process; activating the bonding surface secondactivation process that is di first activation process; and depositingone of a solderable metal on the bonding surface.
 2. The method of claim1, wherein the step of cleaning the bonding surface includes removingorganic contaminants from the bonding surface.
 3. The method of claim 2,wherein the step of removing organic contaminants from the bondingsurface includes using an oxygen plasma to remove the bonding surface.4. The method of claim 1, wherein the step of cleaning the bondingsurface includes removing inorganic contaminants from the bondingsurface.
 5. The method of claim 4, wherein the step of cleaning thebonding surface includes using a buffered oxide etchant.
 6. The methodof claim 1, wherein the step of activating the bonding surface a firsttime includes treating the bonding surface with an activation solutioncomprising palladium.
 7. The method of claim 1, wherein the step ofactivating the bonding surface a second time includes performingnickel—boron electroless plating.
 8. The method of claim 7, furtherincluding performing the step of activating the bonding surface for afirst time ranging between approximately 20 seconds and approximately 50seconds and performing the step of nickel—boron electroless plating fora time ranging between approximately 1.5 minutes and approximately 8minutes.
 9. The method of claim 7, wherein the nickel—boron has athickness ranging between approximately 0.1 microns and approximately0.5 microns.
 10. The method of claim 7, wherein the step of depositingone of a solderable or a wirebondable metal on the bonding surfaceincludes plating nickel—phosphorous on the nickel—boron.
 11. The methodof claim 1, wherein the step of depositing one of a solderable or awirebondable metal on the bonding surface includes depositing a layer ofnickel—phosphorous by electroless plating.
 12. The method of claim 1,wherein the step of depositing one of a solderable or a wirebondablemetal on the bonding surface includes depositing a layer of palladium byelectroless plating.
 13. A method for forming a nickel layer on copper,wherein the copper is disposed on a semiconductor wafer, comprising thesteps of: cleaning a surface of the copper; performing a firstactivation step; performing a second activation step to activate thesurface; and plating one of a solderable or a wirebondable metal on theactivated surface.
 14. The method of claim 13, further including thestep of forming an oxidation protection layer on the one of a solderableor a wirebondable metal.
 15. The method of claim 14 wherein theoxidation protection layer is gold.
 16. The method of claim 13, whereinthe step of performing the first activation step includes activating thesurface in a palladium activation bath and the step of performing thesecond activation step includes depositing a layer of nickel-boron usingelectroless plating.
 17. The method of claim 16, further includingperforming the first and second activation steps and performing the stepof plating one a solderable or a wirebondable metal at temperatures lessthan approximately 90 degrees Celsius.
 18. A semiconductor wafer,comprising: a semiconductor wafer having copper bond pads; a layer ofpalladium disposed on the copper bond pads; a layer of electrolessnickel-boron disposed on the layer of palladium; and one of a solderableor a wirebondable layer disposed on the electroless nickel—boron layer.19. The semiconductor wafer of claim 18, wherein the one of a solderableor a wirebondable layer is a layer comprising electrolessnickel—palladium.
 20. The semiconductor wafer of claim 18, furtherincluding an oxidation protection layer disposed on the layer ofelectroless nickel—boron.
 21. The semiconductor wafer of claim 20,wherein the oxidation protection layer is a layer of gold.
 22. Thesemiconductor wafer of claim 18, wherein the one of a solderable or awirebondable layer is a layer of electroless palladium.